Demonstrated performance

Our ADC technology works well as a network receiver. We've built and tested two network data links.

Prototype network links

Network links need to move information from one computer to another, and they use devices called Serializer/Deserializers (SerDes) to do that. We are building a SerDes receiver for Ethernet applications. Our system operates on the lowest, physical layer of the network stack, mapping electrons into logical values.

SerDes receiver devices implement specific protocols for their particular application. The device needs to meet the minimum specifications of the protocol for things like symbol rate, bit error ratio, and noise tolerance, and then the products are differentiated on criteria such as cost, power consumption, and reliability.

The key technical metric for a physical receiver link operating at a given speed and noise environment is its bit error ratio (BER), or how many bits it receives incorrectly divided by the total number of bits received. Lower is better. Modern network communication uses forward error correction (FEC) schemes that pack messages with extra information to allow the recovery of information over a noisy link. For example, the Ethernet standard IEEE 802.3dj requires 2.4×10⁻⁴ or better to support adequate post-FEC BER with a RS(544,514) forward error correction scheme.

Generation one: NSF SBIR Phase I

Award #2507707 · view award at NSF · completed Jan 2026

The NSF funded our first working SerDes receiver, which we built on printed circuit boards using commercial off-the-shelf discrete components. We achieved PAM4 transmission at 1.2 gigasymbols per second. We built a custom bandpass filter array from standard 5% tolerance passives, deliberately not precision-matched, to show that the architecture is robust against component variation.

Generation one prototype receiver on the bench, built from discrete boards: a DAC board, two hexagonal CLK clock-generation boards, and an AFE and ADC bank connected by coaxial cable. — Generation one prototype on the bench: DAC, clock generation (CLK), and the analog front end and ADC bank (AFE & ADC Bank), linked by a coaxial cable (CHANNEL).

Drift, jitter, and undersampling

We ran the receiver on a degraded clock to show that the system was resilient to the timing distortions encountered at high speed. We sampled the signal below the data rate, with a drifting clock, and high jitter. Any one of these conditions would prevent a traditional receiver from operating.

The goal of this test was to show that the system is resilient to timing imprecision on an otherwise stable system, and it is.

For a 1.2 gigabaud PAM4 signal, we achieved a pre-FEC BER of approximately 5.4×10⁻⁶.

With standard error correction

Applying Reed–Solomon coding across ten billion tested symbols, no codeword block exceeded its correction capacity. Machine-learning signal processing sometimes produces bursty, correlated errors that overwhelm forward error correction. But our system produced errors (corrected by the FEC) that behaved like conventional hardware, showing that our architecture can drop into existing links rather than requiring a new correction scheme.

Generation two: 100G Ethernet class

Summer 2026

We built the second generation prototype to show that the system performs at commercially relevant speeds. We entirely rebuilt the analog front end from catalog RF parts and drove it with PAM signals at different modulations. We ran the system at 56 gigabaud, which at PAM4 produces a lane rate of a 112 Gb/s.

We generated a signal, sent it over copper cables, passed it through our analog front end, and used sampling oscilloscopes to record the measurements.

Eye diagram of a PAM6 signal at 56 gigabaud, sampled at 70 GHz. Five distinct open regions are visible in a vertical stack, one between each adjacent pair of the six amplitude levels. — Eye diagram of transmitter to oscilloscope. PAM6 at 56 GBd, sampled at 70 GHz. The signals bounce between six amplitude levels, resolving into five eye-shaped openings.

Then we made the link worse on purpose. We restricted the input bandwidth and increased the length of the cables, degrading the received signal until the eyes closed completely. A conventional maximum-likelihood sequence detector reading this degraded signal fails outright.

Eye diagram of a PAM6 signal at 56 gigabaud after our cable path, sampled at 33 GHz. The traces form solid horizontal bands with no open regions anywhere in the window. — Eye diagram of degraded link. PAM6 at 56 GBd after our cable path, sampled at 33 GHz. The openings are entirely gone.

Our receiver recovered the information from the degraded PAM6 signal at better than the 2.4×10⁻⁴ pre-FEC BER required for a RS(544,514) scheme from a link a conventional receiver cannot read at all.

For a 56 gigabaud PAM6 signal on our degraded link, we achieved a pre-FEC BER of approximately 1×10⁻⁴.

Ongoing work

The next step is to build an ASIC that receives even faster signals. This will also let us simulate and measure the power consumption of the particular chip.

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